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Preliminary Technical Data
FEATURES
General Low power HDMI/DVI transmitter ideal for portable applications Compatible with HDMI v. 1.3, DVI v. 1.0, and HDCP v. 1.2 Single 1.8 V power supply Video/audio inputs accept logic levels from 1.8 V to 3.3 V 64-lead LFCSP, Pb-free package 76-ball CSP_BGA, Pb-free package Digital video 80 MHz operation supports all resolutions from 480i to 1080i and XGA at 75 Hz Programmable 2-way color space converter Supports RGB, YCbCr, and DDR Supports ITU656-based embedded syncs Automatic input video format timing detection (CEA-861D) Digital audio Supports standard S/PDIF for stereo LPCM or compressed audio up to 192 kHz 8-channel, uncompressed LPCM I2S audio up to 192 kHz Special features for easy system design On-chip MPU with I2C(R) master to perform HDCP operations and EDID reading operations 5 V tolerant I2C and HPD I/Os, no extra device needed No audio master clock needed for supporting S/PDIF and I2S On-chip MPU reports HDMI events through interrupts and registers
High Performance, Low Power HDMITM/DVI Transmitter AD9387NK
FUNCTIONAL BLOCK DIAGRAM
SCL SDA MCL MDA INT
I2C SLAVE HDCP CORE REGISTER CONFIGURATION LOGIC
INTERRUPT HANDLER
HPD
HDCP-EDID MICROCONTROLLER
CLK VSYNC HSYNC DE D[23:0] VIDEO DATA CAPTURE COLOR SPACE CONVERSION 4:2:2 TO 4:4:4 CONVERSION XOR MASK S/PDIF MCLK I2S[3:0] LRCLK SCLK AUDIO DATA CAPTURE
I2C MASTER
DDCSDA DDCSCL
Tx0[1:0] HDMI Tx CORE Tx1[1:0] Tx2[1:0] TxC[1:0]
AD9387NK
06507-001
Figure 1.
APPLICATIONS
Digital video cameras Digital still cameras Personal media players Cellular handsets DVD players and recorders Digital set-top boxes A/V receivers HDMI repeater/splitter
The AD9387NK supports both S/PDIF and 8-channel I2S audio. Its high fidelity, 8-channel I2S can transmit either stereo or 7.1 surround audio at 192 kHz. The S/PDIF can carry stereo LPCM audio or compressed audio, including Dolby(R) Digital, DTS(R), and THX(R). The AD9387NK helps reduce system design complexity and cost by incorporating such features as an internal MPU for HDCP operations, an I2C master for EDID reading, a single 1.8 V power supply, and 5 V tolerance on the I2C and hot plug detect pins. Fabricated in an advanced CMOS process, the AD9387NK is available in a space saving, 76-ball CSP_BGA or 64-lead LFCSP surface-mount package. Both packages are available as Pb-free parts and are specified from -25C to +85C.
GENERAL DESCRIPTION
The AD9387NK is an 80 MHz, high definition multimedia interface (HDMI) v.1.3 transmitter. It supports HDTV formats up to 720p and 1080i and computer graphic resolutions up to XGA (1024 x 768 @ 75Hz). With the inclusion of HDCP, the AD9387NK allows the secure transmission of protected content, as specified by the HDCP v.1.1 protocol.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved.
AD9387NK TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 4 Explanation of Test Levels ........................................................... 4 ESD Caution.................................................................................. 4 Pin Configuration and Function Descriptions............................. 5 Applications Information ................................................................ 7
Preliminary Technical Data
Design Resources ..........................................................................7 Document Conventions ...............................................................7 PCB Layout Recommendations.......................................................8 Power Supply Bypassing ...............................................................8 Digital Inputs .................................................................................8 External Swing Resistor................................................................8 Output Signals ...............................................................................8 Outline Dimensions ..........................................................................9 Ordering Guide .............................................................................9
Rev. PrA | Page 2 of 12
Preliminary Technical Data SPECIFICATIONS
Table 1.
AD9387NK
Parameter DIGITAL INPUTS Input Voltage, High (VIH) Input Voltage, Low (VIL) Input Capacitance DIGITAL OUTPUTS Output Voltage, High (VOH) Output Voltage, Low (VOL) THERMAL CHARACTERISTICS Thermal Resistance JC Junction-to-Case JA Junction-to-Ambient Ambient Temperature DC SPECIFICATIONS Input Leakage Current (IIL) Input Clamp Voltage Differential High Level Output Voltage Differential Output Short-Circuit Current POWER SUPPLY VDD (All) Supply Voltage VDD Supply Voltage Noise Power-Down Current Transmitter Supply Current 2 Transmitter Total Power AC SPECIFICATIONS CLK Frequency TMDS Output CLK Duty Cycle Worst Case CLK Input Jitter Input Data Setup Time Input Data Hold Time TMDS Differential Swing VSYNC and HSYNC Delay from DE Falling Edge VSYNC and HSYNC Delay to DE Rising Edge DE High Time DE Low Time Differential Output Swing Low-to-High Transition Time High-to-Low Transition Time AUDIO AC TIMING Sample Rate I2S Cycle Time I2S Setup Time I2S Hold Time Audio Pipeline Delay
1 2 3
Conditions
Temp Full Full 25C Full Full
AD9387NK-BCPZ-80/AD9387NK-BBCZ-80 Test Level 1 Min Typ Max Unit VI VI V VI VI 1.4 3 VDD - 0.1 0.4 3.5 0.7 V V pF V V
Full 25C 25C 25C
V V V VI V V V IV IV V IV IV VI IV IV IV IV IV VI VI VI VI VI VII VII IV IV IV IV IV
-25 -10
15.2 59 +25
+85 +10
C/W C/W C A V V V A V mV p-p A mA mW MHz % ns ns ns mV UI 3 UI3 UI3 UI3 Ps Ps kHz UI3 ns ns s
-16 mA +16 mA
-0.8 +0.8 AVCC 10 1.71 1.8 10 55 100 13.5 48 1 1 800 80 52 2 1.89 50
Full Full 25C 25C Full 25C 25C Full Full Full
1000 1 1 138
1200
25C 25C 25C 25C I2S and S/PDIF Full 25C 25C 25C 25C
8191
75 75 32 15 0 75
490 490 192 1
See the Explanation of Test Levels section. Using low output drive strength. UI = unit interval.
Rev. PrA | Page 3 of 12
AD9387NK ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter Digital Inputs Digital Output Current Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Maximum Case Temperature Rating 5 V to 0.0 V 20 mA -40C to +85C -65C to +150C 150C 150C
Preliminary Technical Data
EXPLANATION OF TEST LEVELS
I. II. III. IV. V. VI. VII. 100% production tested. 100% production tested at 25C and sample tested at specified temperatures. Sample tested only. Parameter is guaranteed by design and characterization testing. Parameter is a typical value only. 100% production tested at 25C; guaranteed by design and characterization testing. Limits defined by HDMI specification; guaranteed by design and characterization testing.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
Rev. PrA | Page 4 of 12
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 DGND D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 DVDD
AD9387NK
DVDD D0 DE HSYNC VSYNC CLK S/PDIF MCLK I2S0 I2S1 I2S2 I2S3 SCLK LRCLK PVDD PVDD
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
PIN 1 INDICATOR
+
AD9387NK
TOP VIEW (Not to Scale)
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
DVDD D15 D16 D17 D18 D19 D20 D21 D22 D23 MCL MDA SDA SCL DDCSDA DDCSCL
10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K
06507-002
PVDD EXT_SWG AVDD HPD TxC- TxC+ AVDD Tx0- Tx0+ PD/A0 Tx1- Tx1+ AVDD Tx2- Tx2+ INT
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES 1. GND PADDLE ON BOTTOM OF PACKAGE.
BOTTOM VIEW (Not to Scale)
Figure 2. 64-Lead LFCSP Pin Configuration (Top View)
Figure 3. 76-Ball BGA Configuration (Top View)
Table 3. Pin Function Descriptions
Pin No. BGA LFCSP A1 to A10, 39 to 47, B1 to B10, C9, 50 to 63, 2 C10, D9, D10 D1 6 C2 3 C1 4 D2 5 J3 18 K3 E2 E1 20 7 8 Mnemonic D[23:0] Type 1 I Description Video Data Input. Digital input in RGB or YCbCr format. Supports CMOS logic levels from 1.8 V to 3.3 V. Video Clock Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Data Enable Bit for Digital Video. Supports CMOS logic levels from 1.8 V to 3.3 V. Horizontal Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Vertical Sync Input. Supports CMOS logic levels from 1.8 V to 3.3 V. Sets internal reference currents. Place 887 resistor (1% tolerance) between this pin and ground. Hot Plug Detect Signal. This indicates to the interface if the receiver is connected. Supports CMOS logic levels from 1.8 V to 5.0 V. S/PDIF (Sony/Philips Digital Interface) Audio Input. This is the audio input from a Sony/Philips digital interface. Supports CMOS logic levels from 1.8 V to 3.3 V. Audio Reference Clock. 128 x N x fS with N = 1, 2, 3, or 4. Set to 128 x sampling frequency (fS), 256 x fS, 384 x fS, or 512 x fS. Supports CMOS logic levels from 1.8 V to 3.3 V. I2S Audio Data Inputs. These represent the eight channels of audio (two per input) available through I2S. Supports CMOS logic levels from 1.8 V to 3.3 V. I2S Audio Clock. Supports CMOS logic levels from 1.8 V to 3.3 V. Left/Right Channel Selection. Supports CMOS logic levels from 1.8 V to 3.3 V. Power-Down Control and I2C Address Selection. The I2C address and the PD polarity are set by the PD/A0 pin state when the supplies are applied to the AD9387NK. Supports CMOS logic levels from 1.8 V to 3.3 V. Differential Clock Output. Differential clock output at pixel clock rate; TMDS logic level. Differential Output Channel 2. Differential output of the red data at 10x the pixel clock rate; TMDS logic level.
Rev. PrA | Page 5 of 12
CLK DE HSYNC VSYNC EXT_SWG HPD S/PDIF MCLK
I I I I I I I I
F2, F1, G2, G1 H2 H1 J7
9 to 12 13 14 26
I2S[3:0] SCLK LRCLK PD/A0
I I I I
K1, K2 K10, J10
21, 22 30, 31
TxC-/TxC+ Tx2-/Tx2+
O O
06507-003
AD9387NK
BGA K7, K8 K4, K5 H10 J2, J5, J8, K9 D5, D6, D7, E7 G4, G5, J1 Pin No. LFCSP 27, 28 24, 25 32 19, 23, 29 1,48,49 15, 16, 17 Mnemonic Tx1-/Tx1+ Tx0-/Tx0+ INT AVDD DVDD PVDD Type 1 O O O P P P
Preliminary Technical Data
Description Differential Output Channel 1. Differential output of the green data at 10x the pixel clock rate; TMDS logic level. Differential Output Channel 0. Differential output of the blue data at 10x the pixel clock rate; TMDS logic level. Interrupt. Open drain. A 2 k pull-up resistor to the microcontroller I/O supply is recommended. 1.8 V Power Supply for TMDS Outputs. 1.8 V Power Supply for Digital and I/O Power Supply. These pins supply power to the digital logic and I/Os. They should be filtered and as quiet as possible. 1.8 V PLL Power Supply. The most sensitive portion of the AD9387NK is the clock generation circuitry. These pins provide power to the clock PLL. The designer should provide quiet, noise-free power to these pins. Ground. The ground return for all circuitry on-chip. It is recommended that the AD9387NK be assembled on a single, solid ground plane with careful attention given to ground current paths. Serial Port Data I/O. This pin serves as the serial port data I/O slave for register access. Supports CMOS logic levels from 1.8V to 3.3V. Serial Port Data Clock. This pin serves as the serial port data clock slave for register access. Supports CMOS logic levels from 1.8V to 3.3V. Serial Port Data I/O Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data Clock Master to HDCP Key EEPROM. Supports CMOS logic levels from 1.8 V to 3.3 V. Serial Port Data I/O to Receiver. This pin serves as the master to the DDC bus. Supports 5 V CMOS logic level. Serial Port Data Clock to Receiver. This pin serves as the master clock for the DDC bus. Supports 5 V CMOS logic level.
D4, E4, F4, J4, G6, J6, K6, F7, G7, H9, J9 F9 F10 E10 E9 G9 G10
1 2
64, Paddle on bottom side 36 35 37 38 34 33
GND
P
SDA SCL MDA MCL DDCSDA DDCSCL
C2 C2 C2 C2 C2 C2
I = input, O = output, P = power supply, C = control. For a full description of the 2-wire serial interface and its functionality, obtain documentation by contacting NDA from flatpanel_apps@analog.com.
Rev. PrA | Page 6 of 12
Preliminary Technical Data APPLICATIONS INFORMATION
DESIGN RESOURCES
Analog Devices, Inc. evaluation kits, reference design schematics, and other support documentation are available under NDA from flatpanel_apps@analog.com. Other resources include the following: * EIA/CEA-861D, a technical specifications document that describes audio and video infoframes, as well as the E-EDID structure for HDMI. It is available from the Consumer Electronics Association (CEA). HDMI v. 1.3, a defining document for HDMI 1.3, and HDMI Compliance Test Specification v. 1.3. They are available from HDMI Licensing, LLC. HDCP Specification v1.1, the defining technical specifications document for the HDCP v. 1.1. It is available from Digital Content Protection, LLC.
AD9387NK
DOCUMENT CONVENTIONS
In this data sheet, data is represented using the conventions described in Table 4. Table 4. Document Conventions
Data Type 0xNN 0bNN NN Bit Format Hexadecimal (Base 16) numbers are represented using the C language notation, preceded by 0x. Binary (Base 2) numbers are represented using the C language notation, preceded by 0b. Decimal (Base 10) numbers are represented using no additional prefixes or suffixes. Bits are numbered in little endian format; that is, the least significant bit of a byte or word is referred to as Bit 0.
*
*
Rev. PrA | Page 7 of 12
AD9387NK PCB LAYOUT RECOMMENDATIONS
The AD9387NK is a high precision, high speed analog device. For maximum performance, it is important that board layout be optimized.
Other Input Signals
The HPD must be connected to the HDMI connector. A 10 k pull-down resistor to ground is also recommended. The PD/A0 input pin can be connected to GND or supply (through a resistor or a control signal). The device address and power-down polarity are set by the state of the PD/A0 pin when the AD9387NK supplies are applied/enabled. For example, if the PD/A0 pin is low (when the supplies are turned on), then the device address is 0x72 and the power-down is active high. If the PD/A0 pin is high (when the supplies are turned on), the device address is 0x7A and the power down is active low. The SCL and SDA pins should be connected to the I2C master. A pull-up resistor of 2 k to 1.8 V or 3.3 V is recommended.
POWER SUPPLY BYPASSING
It is recommended that each power supply pin be bypassed with a 0.1 F capacitor. The exception is when two or more supply pins are adjacent to each other. For these groupings of powers and grounds, it is necessary to have only one bypass capacitor. The fundamental idea is to have a bypass capacitor within about 0.5 cm of each power pin. Avoid placing the capacitor on the opposite side of the PC board from the AD9387NK, as doing so interposes resistive vias in the path. The bypass capacitors should be located between the power plane and the power pin. Current should flow from the power plane to the capacitor to the power pin. Do not make a power connection between the capacitor and the power pin. Placing a via underneath the capacitor pads, down to the power plane, is generally the best approach. It is particularly important to maintain low noise and good stability of PVDD (the PLL supply). Abrupt changes in PVDD can result in similarly abrupt changes in sampling clock phase and frequency. Such changes can be avoided by careful attention to regulation, filtering, and bypassing. It is best practice to provide separate regulated supplies for each of the analog circuitry groups (AVDD and PVDD). It is also recommended that a single ground plane be used for the entire board. Experience has repeatedly shown that the noise performance is the same or better with a single ground plane. Using multiple ground planes can be detrimental because each separate ground plane is smaller, and long ground loops can result.
EXTERNAL SWING RESISTOR
The external swing resistor must be connected directly to the EXT_SWG pin and ground. The external swing resistor must have a value of 887 (1% tolerance). Avoid running any high speed ac or noisy signals next to, or close to, the EXT_SWG pin.
OUTPUT SIGNALS
TMDS Output Signals
The AD9387NK has three TMDS data channels (0, 1, and 2) that output signals up to 800 MHz, as well as the TMDS output data clock. To minimize the channel-to-channel skew, make the trace length of these signals the same. Also, these traces need a 50 characteristic impedance and should be routed as 100 differential pairs. Best practice recommends routing these lines on the top PCB layer, avoiding the use of vias.
Other Output Signals (non TMDS) DDCSCL and DDCSDA
The DDCSCL and DDCSDA outputs need a minimum amount of capacitance loading to ensure the best signal integrity. The DDCSCL and DDCSDA capacitance loading must be less than 50 pF to meet the HDMI compliance specification. The DDCSCL and DDCSDA must be connected to the HDMI connector, and a pull-up resistor to 5 V is required. The pull-up resistor must have a value between 1.5 k and 2 k.
DIGITAL INPUTS
Video and Audio Data Input Signals
The digital inputs on the AD9387NK are designed to work with signals ranging from 1.8 V to 3.3 V logic level. Therefore, no extra components need to be added when using 3.3 V logic. Any noise that gets onto the clock input (labeled CLK) trace adds jitter to the system. Therefore, minimize the video clock input (Pin 6, CLK) trace length, and do not run any digital or other high frequency traces near it. Make sure to match the length of the input data signals to optimize data capture, especially for high frequency modes, such as 720p or XGA at 75 Hz and double data rate input formats.
INT Pin
The INT pin is an output that should be connected to the system microcontroller. A pull-up resistor to 1.8 V or 3.3 V is required for proper operation; the recommended value is 2 k.
MCL and MDA
The MCL and MDA outputs should be connected to the EEPROM containing the HDCP key (if HDCP is implemented). Pull-up resistors of 2 k are recommended.
Rev. PrA | Page 8 of 12
Preliminary Technical Data OUTLINE DIMENSIONS
9.00 BSC SQ 0.60 MAX 0.60 MAX
49 48
AD9387NK
0.30 0.25 0.18
64 1
PIN 1 INDICATOR
PIN 1 INDICATOR
+
TOP VIEW
8.75 BSC SQ
EXPOSED PAD**
(BOTTO M VIEW)
4.85 4.70 SQ* 4.55
0.45 0.40 0.35
33 32
17
16
1.00 0.85 0.80
12 MAX
0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 0.50 BSC
7.50 REF
SEATING PLANE
0.20 REF
64 LFCSP (LEAD FRAME CHIP SCALE PACKAGE) * COMPLIANT TO JEDEC STANDARDS MO-220-VMMD EXCEPT FOR EXPOSED PAD DIMENSION **Note: PAD is CONNECTED to GND
DIMENSIONS in Millimeters
Figure 4. 64-Lead Lead Frame Chip Scale Package [LFCSP] (CP-64) Dimensions shown in millimeters
6.10 6.00 SQ 5.90 A1 CORNER INDEX AREA
10 9 8 76 5 4 321 A B
BALL A1 PAD CORNER TOP VIEW
4.50 BSC SQ 0.50 BSC
C D E F G H J K
DETAIL A *1.40 MAX
0.75 REF
BOTTOM VIEW
DETAILA
0.15 MIN
0.65 MIN
0.35 SEATING 0.30 PLANE 0.25 BALL DIAMETER *COMPLIANT TO JEDEC STANDARDS MO-225 WITH THE EXCEPTION TO PACKAGE HEIGHT.
COPLANARITY 0.08 MAX
Figure 5. 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 6 mm x 6 mm x 1.4 mm (BC-76) Dimensions shown in millimeters
ORDERING GUIDE
Model AD9387NKBCPZ-80 1 AD9387NKBBCZ-801 AD9387NKBBCZRL-801 AD9387NK/PCB
1
Temperature Range -25C to +85C -25C to +85C -25C to +85C
Package Description 64-Lead Formed Chip Scale Package 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] 76-Ball Chip Scale Package Ball Grid Array [CSP_BGA] Evaluation Board
012006-0
Package Option CP-64 BC-76 BC-76
Z = Pb-free part.
Rev. PrA | Page 9 of 12
AD9387NK NOTES
Rev. PrA | Page 10 of 12
Preliminary Technical Data NOTES
AD9387NK
Rev. PrA | Page 11 of 12
AD9387NK NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
(c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06507-0-12/06(PrA)
Rev. PrA | Page 12 of 12

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